Efficient Area and Speed Optimized Multiplication Technique Using Vedic and Tree Addition Structure

Abstract

Now days we are living in digital world, where all the operations get performed more reliably and with highest accuracy by digital signal processor. The multiplier is the key element of all these processor like Microprocessor, Microcontroller, DSP processor etc. After through study and deep analysis work we have seen that the existing Vedic multiplication hardware has some limitation in terms of area. To overcome these limitations a novel approach has been proposed to design the Vedic multiplier with unique addition structure, which is used to add partially generated products. To meet our major concern ‘Speed’ we need particular high speed multiplier, the speed of multiplier greatly depends upon the type of multiplication technique used in it. We have come up with the idea to merge two different multiplication techniques Vedic and Tree addition structure and these gives us a fast and area efficient multiplication approach.