Robust flip-flop Redesign for Violation Minimization Considering Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI)

Abstract

As the CMOS device becomes smaller, the process and aging variations become one of the major issues for circuit reliability and yield. Thus, a number of studies on the aging effects are currently underway. In this paper, we measure the setup/hold time and the variations considering aging effects such as a hot carrier injection (HCI) and negative bias temperature instability (NBTI) on flip-flop. The measured data was applied to the transistor sizing algorithm. We also have applied aging effects for 5 years with setup time variation reduction to redesign a more robust flip flop. The proposed method analyzed aging effects (NBTI, HCI) for flip flop at the transistor level in 45nm process and used PTM (predictive technology model) SPICE model. The redesigned flip-flop using the proposed algorithm confirmed to have violation minimization after 5 years.