Contention-aware virtual channel assignment in application specific Networks-on-chip

Mona Soleymani, Fatemeh Safinia, Somayyeh Jafarali Jassbi, Midia Reshadi


Nowadays lots of processing elements should be placed on a single chip because of ever complexity of applications. In order to connect this number of processing elements, providing a interconnection infrastructure is essential. Network on Chip (NoC) is used as an efficient architecture for chip multiprocessors, which brings a reasonable performance and high scalability. A relevant challenge in NoC architectures is latency that increased in the presence of network contention. In this paper, we utilized virtual channels in buffer structure of routers. We calculated end to end latency and link utilization in NoCs by considering different numbers of virtual channels ranging from 2 to 5. The simulation results show that using virtual channels for specified routers in 2D mesh 4x4 decreases end to end latency up to 17% . It also improves link utilization and throughput significantly.


Network on Chip; virtual channel; path-based contention; latency

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